Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Analysis of double-gate CMOS for double-pole four-throw RF switch design at 45-nm technology
Journal of Computational Electronics
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Independent gate control in double-gate (DG) devices enhances circuit performance and robustness while substantially reducing leakage and chip area. In this paper, we describe circuit techniques which take advantage of the independent biasing properties of symmetrical and asymmetrical DG devices in design. DG circuits at the 25-nm node are analyzed via mixed-mode numerical simulations using Taurus MEDICI. In dynamic circuits, we give examples of conditional keepers, charge sharing prevention scheme, and static keepers. A conditional keeper can dynamically achieve the optimal strength ratio between keeper and evaluation devices by utilizing the front- and backchannel currents in DG devices. A charge sharing mitigation scheme utilizing the back-gate of a logic transistor is then described. Static data retention scheme in dynamic circuits is proposed. A case study for analog applications using a voltage controlled oscillator (VCO) illustrates the specific advantages of DG devices.