On embedding a graph in the grid with the minimum number of bends
SIAM Journal on Computing
Combinatorial algorithms for integrated circuit layout
Combinatorial algorithms for integrated circuit layout
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
LEDA: a platform for combinatorial and geometric computing
Communications of the ACM
An experimental comparison of four graph drawing algorithms
Computational Geometry: Theory and Applications
Drawing High Degree Graphs with Low Bend Numbers
GD '95 Proceedings of the Symposium on Graph Drawing
Turn-Regularity and Optimal Area Drawings of Orthogonal Representations
Turn-Regularity and Optimal Area Drawings of Orthogonal Representations
An algorithm for optimal two-dimensional compaction of VLSI layouts
Integration, the VLSI Journal
On the Complexity of Orthogonal Compaction
WADS '99 Proceedings of the 6th International Workshop on Algorithms and Data Structures
Optimal Labelling of Point Features in the Slider Model
COCOON '00 Proceedings of the 6th Annual International Conference on Computing and Combinatorics
Graph Drawing Algorithm Engineering with AGD
Revised Lectures on Software Visualization, International Seminar
An Experimental Comparison of Orthogonal Compaction Algorithms (Extended Abstract)
GD '00 Proceedings of the 8th International Symposium on Graph Drawing
ESA '00 Proceedings of the 8th Annual European Symposium on Algorithms
A hybrid genetic algorithm for automatic graph drawing based on the topology-shape-metric approach.
Proceedings of the 12th annual conference on Genetic and evolutionary computation
Minimum depth graph embeddings and quality of the drawings: an experimental analysis
GD'05 Proceedings of the 13th international conference on Graph Drawing
A fuzzy genetic algorithm for automatic orthogonal graph drawing
Applied Soft Computing
Cell-based interconnect migration by hierarchical optimization
Integration, the VLSI Journal
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We consider the two-dimensional compaction problem for orthogonal grid drawings in which the task is to alter the coordinates of the vertices and edge segments while preserving the shape of the drawing so that the total edge length is minimized. The problem is closely related to two-dimensional compaction in vlsi-design and has been shown to be NP-hard. We characterize the set of feasible solutions for the two-dimensional compaction problem in terms of paths in the so-called constraint graphs in x- and y-direction. Similar graphs (known as layout graphs) have already been used for one-dimensional compaction in vlsi-design, but this is the first time that a direct connection between these graphs is established. Given the pair of constraint graphs, the two-dimensional compaction task can be viewed as extending these graphs by new arcs so that certain conditions are satisfied and the total edge length is minimized. We can recognize those instances having only one such extension; for these cases we solve the compaction problem in polynomial time. We transform the geometrical problem into a graph-theoretical one and formulate it as an integer linear program. Our computational experiments show that the new approach works well in practice.