Introduction to algorithms
Balanced block spacing for VLSI layout
Discrete Applied Mathematics - Special issue: graphs in electrical engineering, discrete algorithms and complexity
A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A spacing algorithm for performance enhancement and cross-talk reduction
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A performance-driven MCM router with special consideration of crosstalk reduction
Proceedings of the conference on Design, automation and test in Europe
Low power design challenges for the decade (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Interconnect Analysis and Synthesis
Interconnect Analysis and Synthesis
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Combining wire swapping and spacing for low-power deep-submicron buses
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Minimum crosstalk channel routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A postprocessing algorithm for crosstalk-driven wire perturbation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect sizing and spacing with consideration of coupling capacitance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routability-Driven Placement and White Space Allocation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect power and delay optimization by dynamic programming in gridded design rules
Proceedings of the 19th international symposium on Physical design
Interconnect bundle sizing under discrete design rules
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
The complexity of VLSI power-delay optimization by interconnect resizing
Journal of Combinatorial Optimization
Cell-based interconnect migration by hierarchical optimization
Integration, the VLSI Journal
| Hi-index | 0.00 |
The problem of optimal space allocation among interconnect wires in a VLSI layout, in order to minimize the switching power consumption and the average signal delay, is addressed in this article. We define a Weighted Power-Delay Sum (WPDS) objective function and derive necessary and sufficient conditions for the existence of optimal interwire space allocation, based on the notion of capacitance density. At the optimum, every wire must be in equilibrium of its line-to-line weighted capacitance density on its two opposite sides, and the WPDS of the whole circuit is minimal if and only if capacitance density is uniformly distributed across the entire layout. This condition is shown to be equivalent to all paths of the layout cross-capacitance graph having the same length and all cuts having the same flow. An implementation which has been used in the design of a recent commercial high-end microprocessor and yielded 17% power reduction and 9% delay reduction in top-level interconnects is presented.