RLC interconnect delay estimation via moments of amplitude and phase response
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Clocktree RLC extraction with efficient inductance modeling
DATE '00 Proceedings of the conference on Design, automation and test in Europe
An efficient model for frequency-dependent on-chip inductance
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Proceedings of the 38th annual Design Automation Conference
A factorization-based framework for passivity-preserving model reduction of RLC systems
Proceedings of the 39th annual Design Automation Conference
Challenges in power-ground integrity
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
INDUCTWISE: inductance-wise interconnect simulator and extractor
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An Interconnect Scaling Scheme with Constant On-Chip Inductive Effects
Analog Integrated Circuits and Signal Processing
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
A General S-Domain Hierarchical Network Reduction Algorithm
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches
IEEE Transactions on Computers
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Model-order reductions for MIMO systems using global Krylov subspace methods
Mathematics and Computers in Simulation
Multiple block structure-preserving reduced order modeling of interconnect circuits
Integration, the VLSI Journal
Power-delay optimization in VLSI microprocessors by wire spacing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Parallel solution of large-scale and sparse generalized algebraic riccati equations
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
Parallel algorithms for balanced truncation model reduction of sparse systems
PARA'04 Proceedings of the 7th international conference on Applied Parallel Computing: state of the Art in Scientific Computing
| Hi-index | 0.00 |
From the Publisher:State-of-the-art methods and current perspectives on interconnect The irrepressible march toward smaller and faster integrated circuits has made interconnect a hot topic for semiconductor research. The effects of wire size, topology construction, and network design on system performance and reliability have all been thoroughly investigated in recent years. Interconnect Analysis and Synthesis provides CAD researchers and engineers with powerful, state-of-the-art tools for the analysis, design, and optimization of interconnect. It brings together a wealth of information previously scattered throughout the literature, explaining in depth available analysis techniques and presenting a range of CAD algorithms for synthesizing and optimizing interconnect. Along with examples and results from the semiconductor industry and 150 illustrations, this practical work features:*Models for interconnect as well as devices and the impact of scaling trends*Modern analysis techniques, from matrix reduction and moment matching to transmission-line analysis*An overview of the effects of inductance on on-chip interconnect*Flexible CAD algorithms that can be generalized for different needs, from buffer insertion to wire sizing to routing topology*Emphasis on realistic problem formulations, addressing key design tradeoffs such as those between area and performance