An Interconnect Scaling Scheme with Constant On-Chip Inductive Effects

Authors:
Kaustav Banerjee;Amit Mehrotra
Affiliations:
Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA 93106 kaustav@ece.ucsb.edu;Coordinated Science Lab, University of Illinois at Urbana-Champaign, Urbana IL 61801 amehrotr@uiuc.edu
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2003

Citing 4
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Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects

Proceedings of the 38th annual Design Automation Conference
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Analysis of on-chip inductance effects for distributed RLC interconnects

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Abstract

This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed by ITRS [1], interconnects become extremely resistive and, while inductance effects diminish with scaling but the performance, specifically, delay per unit length, degrades with scaling. The effect of the proposed global interconnect scaling scheme on optimized driver size, interconnect length, delay per unit length and total buffer area is quantified and compared with the unscaled and the ITRS cases. It is shown that the proposed scaling scheme improves the delay per unit length without degrading inductive effects or increasing buffer area with scaling.