SLIM-the translation of symbolic layouts into mask data
DAC '80 Proceedings of the 17th Design Automation Conference
IC mask layout with a single conductor layer
DAC '70 Proceedings of the 7th Design Automation Workshop
Bristle Blocks: A silicon compiler
DAC '79 Proceedings of the 16th Design Automation Conference
Topological analysis for VLSI circuits
DAC '79 Proceedings of the 16th Design Automation Conference
Improving virtual-grid compaction through grouping
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
KAHLUA: a hierarchical circuit disassembler
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Automated layout generation using gate matrix approach
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
PAMS: an expert system for parameterized module synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A two-dimensional topological compactor with octagonal geometry
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Process independent constraint graph compaction
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Symbolic layout compaction review
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
MCNC's vertically integrated symbolic design system
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Auto-interactive schematics to layout translation
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Generalised CMOS—a technology independent CMOS IC design style
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Effective use of virtual grid compaction in macro-module generators
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Minplex—a compactor that minimizes the bounding rectangle and individual rectangles in a layout
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Dual quadtree representation for VLSI designs
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
CSC '85 Proceedings of the 1985 ACM thirteenth annual conference on Computer Science
ACM '86 Proceedings of 1986 ACM Fall joint computer conference
POPL '83 Proceedings of the 10th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Rapid Prototyping of High-Speed Communications Chips
IEEE Design & Test
Optimal Joining of Compacted Cells
IEEE Transactions on Computers
A vertically integrated VLSI design environment
DAC '83 Proceedings of the 20th Design Automation Conference
Experiments with the SLIM Circuit Compactor
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
Plowing: Interactive stretching and compaction in magic
DAC '84 Proceedings of the 21st Design Automation Conference
The rectangle placement language
DAC '84 Proceedings of the 21st Design Automation Conference
MGX: An integrated symbolic layout system for VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
A layout synthesis system for NMOS gate-cells
DAC '82 Proceedings of the 19th Design Automation Conference
A symbolic design system for integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
VLSI tools and architectures: Putting the new technology to work
CSC-83 Proceedings of the 1983 computer science conference
IBM Journal of Research and Development
Constraint solver for generalized IC layout
IBM Journal of Research and Development
An algorithm for optimal two-dimensional compaction of VLSI layouts
Integration, the VLSI Journal
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Free form or “stick” type symbolic layout provides a means of simplifying the design of IC subcircuits. To successfully utilize this style of layout, a complete design approach and the necessary tools to support this methodology are required. In particular, one of the requirements of such a design method is the ability to “compact” the loosely specified topology to create a set of valid mask data. This paper presents a new compaction strategy which uses the concept of a virtual grid. The compaction algorithm using the virtual grid is both simple and fast, an attribute which allows the designer to conveniently interact with the algorithm to optimize a layout. In addition to the compaction algorithm, methods used to create large building blocks will be described. The work described here is part of a complete symbolic layout system called MULGA which is written in the C programming language and resides on the UNIX operating system.