Constraint solver for generalized IC layout

  • Authors:
  • Peter W. Cook

  • Affiliations:
  • IBM Research Division, P.O. Box 218, Yorktown Heights, New York

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 1984

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Abstract

This paper presents a constraint solver suitable for use in a general symbolic IC layout system. The essential features of the constraint solver, which is intended to place few restrictions on the source of the constraints to be solved, are that it accommodate mixed equality and inequality constraints, that it allow selective "maximization" of variables, that it proceed with any number of variables given user-defined values, and that it fail to produce a solution only when no solution exists. These features all flow from the desire to provide a constraint solver suitable for use in an "open" system, in which there are no restrictions on the form or order of the constraints. The algorithm presented meets these objectives while remaining reasonable in its use of storage and time. An extension to the class of constraints acceptable by the constraint solver is presented; the extension of the system to this added constraint class has yet to be done.