An algorithm to compact a VLSI symbolic layout with mixed constraints

Authors:
Y. Z. Liao;C. K. Wong
Affiliations:
IBM Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Thomas J. Watson Research Center, Yorktown Heights, New York
Venue:
DAC '83 Proceedings of the 20th Design Automation Conference
Year:
1983

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Abstract

A popular algorithm to compact a VLSI symbolic layout is to use a graph algorithm similar to finding the 'longest-path' in a network. The algorithm assumes that the spacing constraints on the mask elements are of the lower-bound type. However, to enable the user to have close control over the compaction result, a desired symbolic layout system should allow the user to add either the equality or the upper-bound constraints on selected pairs of mask elements as well. This paper proposes an algorithm which uses a graph-theoretic approach to solve efficiently the compaction problem with mixed constraints.