VLSI design process

  • Authors:
  • Vishwani Agrawal;Samuel H. C. Poon

  • Affiliations:
  • AT&T Bell Laboratories, Murray Hill, New Jersey;AT&T Bell Laboratories, Murray Hill, New Jersey

  • Venue:
  • CSC '85 Proceedings of the 1985 ACM thirteenth annual conference on Computer Science
  • Year:
  • 1985

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Abstract

This paper presents a review of the computer-aided design of VLSI devices. For illustrative purposes, the design methodology is modeled as an idealized two-level process. In the first level, known as the functional level, the requirements of the device are converted into logic description and tests are generated. The second level consists of the physical design involving layout. In each level, our model represents the design as a feedback process with verification closing the loop on synthesis or layout. While the future design methodology might be closer to this idealization, today's design process differs significantly depending upon the specific design environment.