A vertically integrated VLSI design environment
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
Magic's incremental design-rule checker
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
A symbolic design system for integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
Plowing: modifying cells and routing 45:9D - layouts
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A categorized bibliography on incremental computation
POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
An investigation of iterative routing algorithms
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A channelless, multilayer router
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
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The Magic layout editor provides a new operation called plowing, for stretching and compacting Manhattan VLSI layouts. Plowing works directly on the mask-level representation of a layout, allowing portions of it to be rearranged while preserving connectivity and layout-rule correctness. The layout and connectivity rules are read from a file, so plowing is technology independent. Plowing is fast enough to be used interactively. This paper presents the plowing operation and the algorithm used to implement it.