Space efficient algorithms for VLSI artwork analysis
DAC '83 Proceedings of the 20th Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
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This paper describes the virtual grid compaction system provided by the IDA environment. The system facilitates the development and use of silicon generators, and supports their porting to new environments. A generator is a program that accepts parameters and produces good quality silicon layouts for small to medium size subcircuits, such as counters, registers, multipliers, etc. The system makes use of the “i” language for layout descriptions, the C language for algorithmic descriptions, a virtual grid to lambda grid compactor, and a tool for decompacting symbols so that they will match exactly, or with minimal routing between them. There are several ways to use the system, depending on the amount of flexibility needed. This system has been used to create a library of generators, and is flexible enough to handle a wide range of practical layout problems.