Graph-optimization techniques for IC layout and compaction

Authors:
Gershon Kedem;Hiroyuki Watanabe
Affiliations:
Computer Science Department, University of Rochester, Rochester, NY;Computer Science Department, University of Rochester, Rochester, NY
Venue:
DAC '83 Proceedings of the 20th Design Automation Conference
Year:
1983

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Abstract

This paper describes a new approach for IC layout and compaction. The compaction problem is translated into a mixed integer-linear programming problem of a very special form. A graph based optimization algorithm is used to solve the resulting problem. An experimental program that uses the above techniques is described. The program could be used either as an aid to hand layout or as the bottom part of an automatic layout generation program.