The art of computer programming, volume 3: (2nd ed.) sorting and searching
The art of computer programming, volume 3: (2nd ed.) sorting and searching
Graph-optimization techniques for IC layout and compaction
DAC '83 Proceedings of the 20th Design Automation Conference
Improved compaction by minimized length of wires
DAC '83 Proceedings of the 20th Design Automation Conference
A hiererachical, error-tolerant compactor
DAC '84 Proceedings of the 21st Design Automation Conference
An O (N log N) algorithm for Boolean mask operations
DAC '81 Proceedings of the 18th Design Automation Conference
A symbolic design system for integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
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In this paper we present a hierarchical symbolic layout system. This system combines a procedural layout language with a symbolic layout editor, on-line incremental netlist extraction with connectivity checking, compaction and wire length minimization. The compactor features overlapping cells, wire segments that cross cell boundaries and connecting inside cells, and sliding contacts. A new model for wire length minimization is proposed.