A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
IC mask layout with a single conductor layer
DAC '70 Proceedings of the 7th Design Automation Workshop
Microelectronics and printed circuits: Problems and their solutions
DAC '68 Proceedings of the 5th annual Design Automation Workshop
A computational theory of planar imbedding
A computational theory of planar imbedding
An efficient planarity algorithm
An efficient planarity algorithm
On the topological aspects of the circuit layout problem
DAC '76 Proceedings of the 13th Design Automation Conference
Software engineering and scale-free networks
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
Software engineering and scale-free networks
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics - Special issue on cybernetics and cognitive informatics
| Hi-index | 0.00 |
The use of topological methods for the circuit layout problem is surveyed first. In the second part an improved model is proposed, which allows pin and gate assignment in function of the layout.