The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing
DAC '81 Proceedings of the 18th Design Automation Conference
An automatic/interactive layout planning system for arbitrarily-sized rectangular building blocks
DAC '81 Proceedings of the 18th Design Automation Conference
Methods for hierarchical automatic layout of custom LSI circuit masks
DAC '78 Proceedings of the 15th Design Automation Conference
DAC '82 Proceedings of the 19th Design Automation Conference
Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
Semi-detailed bus routing with variation reduction
Proceedings of the 2007 international symposium on Physical design
A simultaneous bus orientation and bused pin flipping algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A new physical routing approach for robust bundled signaling on NoC links
Proceedings of the 20th symposium on Great lakes symposium on VLSI
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In LSI and VLSI layout, certain categories of signal nets, e.g. critical nets, power buses and data buses, require special attention during routing. In data bus routing the goal is to maximize the commonality of the routing paths comprising the bus, without unnecessarily lengthening individual routing paths. A topological data bus router has been implemented in the Hughes Automated Layout system and is the subject of this paper.