Introduction to VLSI Systems
A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
A min-cut placement algorithm for general cell assemblies based on a graph representation
DAC '79 Proceedings of the 16th Design Automation Conference
Introduction to silicon compilation
DAC '79 Proceedings of the 16th Design Automation Conference
Bristle Blocks: A silicon compiler
DAC '79 Proceedings of the 16th Design Automation Conference
Silicon compilation-a hierarchical use of PLAs
DAC '79 Proceedings of the 16th Design Automation Conference
Programmed Logic Array Optimization
IEEE Transactions on Computers
Hardware Algorithms for Nonnumeric Computation
IEEE Transactions on Computers
The CMU RT-CAD system: an innovative approach to computer aided design
AFIPS '76 Proceedings of the June 7-10, 1976, national computer conference and exposition
Clairvoyant: a synthesis system for production-based specification
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A system to lay out custom circuits that recognize regular languages can be a useful VLSI design automation tool. This paper describes the algorithms used in an implementation of a regular expression compiler. Layouts that use a network of programmable logic arrays (PLA's) have smaller areas than those of some other methods, but there are the problems of partitioning the circuit and then placing the individual PLA's. Regular expressions have a structure which allows a novel solution to these problems: dynamic programming can be used to find layouts which are in some sense optimal. Various search pruning heuristics have been used to increase the speed of the compiler and the experience with these is reported in the conclusions.