Connectivity biased channel construction and ordering for building-block layout

Authors:
H. Cai
Affiliations:
Delft University of Technology, Department of Electrical Engineering, Delft, The Netherlands
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

Citing 3
Cited 2

A subjective review of compaction (tutorial session)

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Methods for hierarchical automatic layout of custom LSI circuit masks

DAC '78 Proceedings of the 15th Design Automation Conference
A min-cut placement algorithm for general cell assemblies based on a graph representation

DAC '79 Proceedings of the 16th Design Automation Conference

Integrated placement for mixed macro cell and standard cell designs

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
CHEOPS: an integrated VLSI floor planning and chip assembly system implemented in object oriented LISP

EURO-DAC '90 Proceedings of the conference on European design automation

Quantified Score

Hi-index	0.00

Visualization

Abstract

A number of techniques are presented for the construction and ordering of routing channels for building-block layout. First, before the routing channels are defined the placement is modified such that proper routing space is assigned between the circuit blocks. Second, a channel graph is constructed on which the global routing will be performed. Finally, after the global routing a feasible routing order is assigned to the channels. In contrast to other works, the algorithms use both the geometrical data (the placement) and the topological data (the connectivity) to decide which channel structure should be chosen from the feasible set.