Decomposition of logic networks into silicon

Authors:
Steven T. Healey;Daniel D. Gajski
Affiliations:
Department of Computer Science, University of IIlinois at Urbana-Champaign, Urbana, IL;Department of Computer Science, University of IIlinois at Urbana-Champaign, Urbana, IL
Venue:
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Year:
1985

Citing 5
Cited 3

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Abstract

This paper describes a module compiler for decomposing arbitrary functional units of any complexity into abstract cells for customized VLSI layouts. The compiler takes the description of a functional unit as input and builds a dependence graph representation. The graph is then partitioned and the nodes are packed into abstract cell output descriptions. The algorithm will tailor the design to a given area and aspect ratio. Routing is done automatically through the cells.