An efficient heuristic for standard-cell placement
Integration, the VLSI Journal
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
PROUD: A Sea-Of-Gates Placement Algorithm
IEEE Design & Test
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
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A fast placement algorithm is presented for large Standard-Cell and Sea-of-Gates placement problems. The time complexity of the algorithm is O (n log2n). In comparison with a state of the art conventional placement and routing tool it yields more than 10 % smaller layouts with significantly better timing characteristics. The method underlying this algorithm uses a quadratic cost function of the wire length and has a wider applicability than existing methods. We expect that with this algorithm high quality placements upto 100000 cells can be obtained.