Prime: a timing-driven placement tool using a piecewise linear resistive network approach
DAC '93 Proceedings of the 30th international Design Automation Conference
Compression-relaxation: a new approach to performance driven placement for regular architectures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Timing driven placement for large standard cell circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Hierarchical interconnection structures for field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Physical hierarchy generation with routing congestion control
Proceedings of the 2002 international symposium on Physical design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A novel net weighting algorithm for timing-driven placement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On the Interaction Between Power-Aware FPGA CAD Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
Proceedings of the 2004 international symposium on Low power electronics and design
Routability-driven placement and white space allocation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A novel methodology for designing high-performance and low-energy FPGA routing architecture
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Congestion estimation during top-down placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimality and scalability study of existing placement algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The popularity of reconfigurable logic devices and portable hardwaredemands ever increasing power saving schemes for low power designs. Thispaper looks at the CAD design process of reconfigurable devices andpresents a novel method to gain power savings during the placement stage ofthe CAD flow. The proposed system modeled the number of switches used inthe circuit and employed simulated annealing algorithm to reduce theoverall routing power. The system was tested against 8 large benchmarkcircuits. It was able to achieve a routing power saving of up to 18%compared with cases without modeling the switches.