Postplacement voltage assignment under performance constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Application-driven floorplan-aware voltage island design
Proceedings of the 45th annual Design Automation Conference
Incremental improvement of voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application-driven voltage-island partitioning for low-power system-on-chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interstratum connection design considerations for cost-effective 3-D system integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy efficient mapping and voltage islanding for regular NoC under design constraints
International Journal of High Performance Systems Architecture
Post-placement voltage island generation for timing-speculative circuits
Proceedings of the 50th Annual Design Automation Conference
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High power consumption not only leads to short battery life for hand-held devices but also causes on-chip thermal and reliability problems in general. As power consumption is proportional to the square of supply voltage, reducing supply voltage can significantly reduce power consumption. Multi-supply voltage (MSV) has previously been introduced to provide finer grain power and performance tradeoff. In this paper, we propose a methodology on top of a set of algorithms to exploit nontrivial voltage island boundaries for optimal power versus design-cost tradeoff under performance requirement. Our algorithms are efficient, robust, and error-bounded and can be flexibly tuned to optimize for various design objectives (e.g., minimal power within a given number of voltage islands, or minimal fragmentation in voltage islands within a given power bound) depending on the design requirement. Our experiment on real industry designs shows a tenfold improvement of our method over current logical-boundary-based industry approach.