Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Calibration of rent's rule models for three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3D Processing Technology and Its Impact on iA32 Microprocessors
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Analytical Model for the Propagation Delay of Through Silicon Vias
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits
Microelectronics Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Emerging 3-D multistrata system integration offers the capability for high density interstratum interconnects that have short lengths and low parasitics. However, 3-D integration is only one way to accomplish system integration and it must compete against established system integration options such as system-on-a-chip (SoC) and system-in-a-package. We discuss multiple tradeoffs that need to be carefully considered for choosing 3-D integration over other integration schemes. The first step toward enabling 3-D design is characterizing the new interstratum connection elements, microconnects and through-Si vias, in a bonded 3-D technology. We have used both analytical- and simulation-based approaches to analyze the parasitic characteristics of interstratum connections between bonded 3-D stratum, and have compared the interstratum power and performance with SoC global interconnects, taking into account the impact of technology scaling. The specific elements in an interstratum connection and their electrical properties strongly depend on the choice of 3-D integration architecture, such as face-to-face, back-to-face, or the presence of redistribution layer for bonding. We present an adaptive interstratum IO circuit technique to drive various types of interstratum connections and thus enable 3-D die reuse across multiple 3-D chips. The 3-D die/intellectual property reuse concept with the adaptive interstratum IO design can be applied to design 3-D ready dice to amortize additional 3-D costs associated with strata design, test, and bonding process.