Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
ClariNet: a noise analysis tool for deep submicron design
Proceedings of the 37th Annual Design Automation Conference
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Driver modeling and alignment for worst-case delay noise
Proceedings of the 38th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact and efficient crosstalk estimation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Signal integrity management in an SoC physical design flow
Proceedings of the 2003 international symposium on Physical design
Layer assignment for crosstalk risk minimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Coupling aware timing optimization and antenna avoidance in layer assignment
Proceedings of the 2005 international symposium on Physical design
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One of the critical challenges in today's high performance IC design is to take noise into account as early as possible in the design cycle. Current noise analysis tools [1, 7} are effective at analyzing and identifying noise in the post-route design stage when detailed parasitic information is available. However, noise problems identified at this stage of design cycle are very difficult to fix due to the limited flexibility in the design and may cause additional iterations of routing and placement, adding costly delays to time-to-market. In this paper, we introduce an estimated, congestion-based pre-route noise analysis approach to identify post-route noise failures before the actual detailed route is completed. We introduce new methods to estimate the RC characteristics of victim and aggressor lines, their coupling capacitances and the aggressor transition times before routing is performed. The approach is based on congestion information obtained from a global router. Since the exact location and relative position of wires in the design is not yet available at this point, we propose a novel probabilistic method for capacitance extraction. We present results on two high performance microprocessors in 0.18&mgr; technology that demonstate the effectiveness of the proposed approac.