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DAC '97 Proceedings of the 34th annual Design Automation Conference
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ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
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ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 37th Annual Design Automation Conference
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Proceedings of the 37th Annual Design Automation Conference
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Proceedings of the 2003 international symposium on Physical design
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Proceedings of the 2003 international symposium on Physical design
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Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
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Analog Integrated Circuits and Signal Processing
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
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ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
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Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Victim alignment in crosstalk aware timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 19th ACM Great Lakes symposium on VLSI
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present a new approach to model the impact of cross-coupling noise on interconnect delay. We introduce a new linear driver model that accurately models the noise pulse induced on a switching signal net due to cross coupling capacitance. The proposed model effectively captures the non-linear behavior of the victim driver gate during the transition and has an average error below 8% whereas the traditional approach using a Thevenin model incurs an average error of 48%. We also discuss the worst case alignment of the aggressor net transitions with respect to the victim net transition, emphasizing the need to maximize not merely the delay of the interconnect alone but the combined delay of the interconnect and receiver gate. We show that the worst case alignment of an aggressor net transition is a function of the receiver gate output loading, victim transition edge rate, and the noise pulse width and height and hence propose a pre-characterization approach to efficiently predict the worst-case alignment. The proposed methods were implemented in an industrial noise analysis tool called ClariNet. Results on industrial designs are presented to demonstrate the effectiveness of our approach.