Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A bus delay reduction technique considering crosstalk
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Inductance 101: analysis and design issues
Proceedings of the 38th annual Design Automation Conference
Driver modeling and alignment for worst-case delay noise
Proceedings of the 38th annual Design Automation Conference
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Interconnect modeling and optimization in deep sub-micron technologies
Interconnect modeling and optimization in deep sub-micron technologies
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Timing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance computation for precharacterized CMOS gates with RC loads
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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This work introduces an extended linear pattern-dependent model for high-level signal delay estimation in high-speed very deep submicron point-to-point interconnects. The proposed model accurately predicts the delay in both inductively and capacitively coupled lines for the complete set of the switching patterns and not only for capacitively coupled lines or worst-case delay as in previous works. We also consider process variations in the formulation of the model and propose a moment-based approach for the inclusion of variations. The accuracy of the model has been assessed by means of extensive experiments. Moreover, we show how the model can be applied at high levels of abstraction in order to explore coding-based alternatives to improve throughput.