A Power-Efficient, Low-Complexity, Memoryless Coding Scheme for Buses with Dominating Inter-Wire Capacitances

Authors:
Tina Lindkvist;Jacob Lofvenberg;Henrik Ohlsson;Kenny Johansson;Lars Wanhammar
Affiliations:
Linköpings Universitet, Sweden;Linköpings Universitet, Sweden;Linköpings Universitet, Sweden;Linköpings Universitet, Sweden;Linköpings Universitet, Sweden
Venue:
IWSOC '04 Proceedings of the System-on-Chip for Real-Time Applications, 4th IEEE International Workshop
Year:
2004

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Abstract

In this paper we present a simplified model of parallel, on-chip buses, motivated by the movement toward CMOS technologies where the ratio between inter-wire capacitance and wire-to-ground capacitance is very large. We also introduce a ternary bus state representation, suitable for the bus model.Using this representation we propose a coding scheme without memory which reduces energy dissipation in the bus model by approximately 20-30% compared to an uncoded system.At the same time the proposed coding scheme is easy to realize, in terms of standard cells needed, compared to several previously proposed solutions.