Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
COMPASS - A tool for evaluation of compression strategies for embedded processors
Journal of Systems Architecture: the EUROMICRO Journal
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Network-on-Chip interconnect for pairing-based cryptographic IP cores
Journal of Systems Architecture: the EUROMICRO Journal
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We present Bus Switching Activity Analyser (BSAA), a switching activity analysis and visualisation tool for SoC power optimisation. BSAA reads switching metrics from RTL simulation, reporting the most active buses and hierarchies. Buses with typical address and data bus traffic are identified automatically. The tool can process multiple simulation runs simultaneously, analysing how switching varies with input data or software code. BSAA complements commercial tools, helping the designer find opportunities to apply power-saving techniques. To illustrate BSAA’s powerful features, we analyse switching in an MP3 decoder design using several audio inputs and in a microcontroller running a suite of software tasks. We demonstrate the tool’s usefulness by applying it in the power optimisation of a small MPSoC, obtaining on average a 60% reduction in dynamic power across five software tasks and identifying opportunities to reduce static power.