Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Selective instruction compression for memory energy reduction in embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Compiler-driven cached code compression schemes for embedded ILP processors
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
Cached-code compression for energy minimization in embedded processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A code decompression architecture for VLIW processors
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
A Simple and Fast Scheme for Code Compression for VLIW Processors
DCC '03 Proceedings of the Conference on Data Compression
A Multi-Level Memory System Architecture for High-Performance DSP Applications
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Code Compression Based on Operand-Factorization for VLIW Processors
DCC '04 Proceedings of the Conference on Data Compression
IEEE Transactions on Computers
Multi-profile based code compression
Proceedings of the 41st annual Design Automation Conference
An Instruction Set Architecture Based Code Compression Scheme for Embedded Processors
DCC '05 Proceedings of the Data Compression Conference
A code compression advisory tool for embedded processors
Proceedings of the 2005 ACM symposium on Applied computing
SAMC: a code compression algorithm for embedded processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BSAA: a switching activity analysis and visualisation tool for soc power optimisation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Studying the code compression design space - A synthesis approach
Journal of Systems Architecture: the EUROMICRO Journal
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A major concern of embedded system architects is the design for low power. We address one aspect of the problem in this paper, namely the effect of executable code compression. There are two benefits of code compression - firstly, a reduction in the memory footprint of embedded software, and secondly, potential reduction in memory bus traffic and power consumption. Since decompression has to be performed at run time it is achieved by hardware. We describe a tool called COMPASS which can evaluate a range of strategies for any given set of benchmarks and display compression ratios. Also, given an execution trace, it can compute the effect on bus toggles, and cache misses for a range of compression strategies. The tool is interactive and allows the user to vary a set of parameters, and observe their effect on performance. We describe an implementation of the tool and demonstrate its effectiveness. To the best of our knowledge this is the first tool proposed for such a purpose.