Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Software Controlled Reconfigurable On-Chip Memory for High Performance Computing
IMS '00 Revised Papers from the Second International Workshop on Intelligent Memory Systems
Bandwidth tracing arbitration algorithm for mixed-clock SoC with dynamic priority adaptation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
COMPASS - A tool for evaluation of compression strategies for embedded processors
Journal of Systems Architecture: the EUROMICRO Journal
Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms
Proceedings of the 48th Design Automation Conference
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With the explosion of Digital Signal Processor (DSP) applications, there is a constant requirement for increased processing capability. This in turn is requiring rapid performance scaling in both operations per cycle and cycles per second, both of which result in increased MIPS/MMACS/MFLOPs. The memory system has to sustain the increased frequency and bandwidth demands in order to meet the data requirements of the DSP. Traditionally, DSP system architectures have on-chip addressable RAM, which is accessible by both the central processing unit (CPU) and the direct memory access (DMA). However, RAM frequencies are not scaling along with CPU clock rates, and as a result only relatively small RAM sizes are able to meet the frequency goals. This is in direct contrast to the increasing program size requirements seen by DSP applications, which in turn require even more on-chip RAM. This paper proposes a solution which has caches and RAMs coexisting in a homogeneous environment and working seamlessly together allowing high frequencies while still maintaining the DSP goals of low cost and low power. This multi-level memory system architecture has been implemented on the Texas Instruments (TI) TMS320C6211 C6x DSP.