Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Compiler techniques for code compaction
ACM Transactions on Programming Languages and Systems (TOPLAS)
A code decompression architecture for VLIW processors
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
A Simple and Fast Scheme for Code Compression for VLIW Processors
DCC '03 Proceedings of the Conference on Data Compression
Enhancing the instruction fetching mechanism using data compression
Enhancing the instruction fetching mechanism using data compression
Code Compression Based on Operand-Factorization for VLIW Processors
DCC '04 Proceedings of the Conference on Data Compression
SAMC: a code compression algorithm for embedded processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
COMPASS - A tool for evaluation of compression strategies for embedded processors
Journal of Systems Architecture: the EUROMICRO Journal
Studying the code compression design space - A synthesis approach
Journal of Systems Architecture: the EUROMICRO Journal
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We present a tool which is designed to be used as a code compression advisory system for object code to be run on an embedded processor. All the compression schemes support run-time random decompression. Given the machine instruction set architecture, the encoding of instructions, and a set of object programs to be compressed, the tool analyzes the code, gathers statistics about static instruction frequencies and other relevant information, and performs a relative evaluation of a suite of compression strategies. The tool produces as output, the sizes of the compressed code, the Line Address Table (if one is required), and the dictionary (if there is only one) or the sizes of all dictionaries if there are several, for various choices of parameters input by the user. The final result helps one to decide a code compression strategy for the input processor. We have used the tool to evaluate alternate schemes for a suite of benchmarks for the TI TMS320C62x instruction set architecture and the Intel StrongARM processor and report results.