Executing compressed programs on an embedded RISC architecture
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Productivity issues in high-level design: are tools solving the real problems?
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Procedure based program compression
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Selective instruction compression for memory energy reduction in embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Code compression for low power embedded system design
Proceedings of the 37th Annual Design Automation Conference
Cached-code compression for energy minimization in embedded processors
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Design of an one-cycle decompression hardware for performance increase in embedded systems
Proceedings of the 39th annual Design Automation Conference
Compiler Design Handbook: Optimizations and Machine Code Generation
Compiler Design Handbook: Optimizations and Machine Code Generation
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators
Journal of VLSI Signal Processing Systems
CoCo: a hardware/software platform for rapid prototyping of code compression technologies
Proceedings of the 40th annual Design Automation Conference
Code density optimization for embedded DSP processors using data compression techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A Simple and Fast Scheme for Code Compression for VLIW Processors
DCC '03 Proceedings of the Conference on Data Compression
Power compiler: a gate-level power optimization and synthesis system
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Survey of code-size reduction methods
ACM Computing Surveys (CSUR)
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Code Compression Based on Operand-Factorization for VLIW Processors
DCC '04 Proceedings of the Conference on Data Compression
A hamming distance based VLIW/EPIC code compression technique
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
An Instruction Set Architecture Based Code Compression Scheme for Embedded Processors
DCC '05 Proceedings of the Data Compression Conference
A code compression advisory tool for embedded processors
Proceedings of the 2005 ACM symposium on Applied computing
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
A bitmask-based code compression technique for embedded systems
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
COMPASS - A tool for evaluation of compression strategies for embedded processors
Journal of Systems Architecture: the EUROMICRO Journal
Efficient Placement of Compressed Code for Parallel Decompression
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Code decompression unit design for VLIW embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Introduction to High-Level Synthesis
IEEE Design & Test
An Efficient Tool-Chain for Analyzing Tradeoffs of Code Compression Schemes in Embedded Processors
RTCSA '12 Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
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Embedded domain has witnessed the application of different code compression methodologies on different architectures to bridge the gap between ever-increasing application size and scarce memory resources. Selection of a code compression technique for a target architecture requires a detailed study and analysis of the code compression design space. There are multiple design parameters affecting the space, time, cost and power dimensions. Standard approaches of exploring the code compression design space are tedious, time consuming, and almost impractical with the increasing number of proposed compression algorithms. This is one of the biggest challenges faced by an architect trying to adopt a code compression methodology for a target architecture. We propose a novel synthesis based tool-chain for fast and effective exploration of the code compression design space and for evaluation of the tradeoffs. The tool-chain consists of a frontend framework that works with different compression/decompression schemes and a backend with high-level-synthesis, logic-synthesis, and power estimation tools to output the critical design parameters. We use the tool-chain to effectively analyze different code compression/decompression schemes of varying complexities.