Network-on-Chip interconnect for pairing-based cryptographic IP cores
Journal of Systems Architecture: the EUROMICRO Journal
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On-chip interconnection networks (OCINs) in many-core systems are key to the system’s performance scalability. OCIN design constraints are governed by power, cost, latency, ease of routing, as well as others. As chips with 16 cores are around the corner, we focus on 16-core systems and consider 9 OCINs for 16-core MPSoCs. A key requirement of real time embedded systems is dependable timeliness. This directly translates into primarily, low diameter, and secondary, average distance requirements. As these are immediately linked to the network’s topology in general, and the node degree and total link cost in particular, we also monitor the node degree and total link cost. For these 9 OCINs, we derive their diameters, average delays, node degrees, and total link costs. We compare these OCINs with respect to these network attributes in an attempt to identify the most suitable OCIN for 16-core MPSoC systems.