A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Networks on chip
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Topology optimization for application-specific networks-on-chip
Proceedings of the 2004 international workshop on System level interconnect prediction
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Fault tolerance overhead in network-on-chip flow control schemes
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
A unified approach to constrained mapping and routing on network-on-chip architectures
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Designing application-specific networks on chips with floorplan information
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
NoC Design and Implementation in 65nm Technology
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
Distributed flit-buffer flow control for networks-on-chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processors
Proceedings of the 2nd International Workshop on Network on Chip Architectures
An outlook on design technologies for future integrated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Mesh-of-trees and alternative interconnection networks for single-chip parallelism
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Avoiding cache thrashing due to private data placement in last-level cache for manycore scaling
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Virtual point-to-point connections for NoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Networks on Chips: from research to products
Proceedings of the 47th Design Automation Conference
aelite: a flit-synchronous network on chip with composable and predictable services
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring programming model-driven QoS support for NoC-based platforms
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the Third International Workshop on Network on Chip Architectures
VLSI micro-architectures for high-radix crossbar schedulers
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
A low-swing crossbar and link generator for low-power networks-on-chip
Proceedings of the International Conference on Computer-Aided Design
Viper: virtual pipelines for enhanced reliability
Proceedings of the 39th Annual International Symposium on Computer Architecture
Efficient genetic based topological mapping using analytical models for on-chip networks
Journal of Computer and System Sciences
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Designing on-chip networks for throughput accelerators
ACM Transactions on Architecture and Code Optimization (TACO)
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Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of NoC-based interconnect design in nanometer CMOS. The authors present experimental results from fully working 65-nm NoC designs and a detailed scalability analysis.