Data structures and network algorithms
Data structures and network algorithms
A linear-time heuristic for improving network partitions
25 years of DAC Papers on Twenty-five years of electronic design automation
A new approach to the multiport memory allocation problem in data path synthesis
Integration, the VLSI Journal
A scheduling algorithm for multiport memory minimization in datapath synthesis
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
A grid-based approach for connectivity binding with geometric costs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Low-energy embedded FPGA structures
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Integrating floorplanning in data-transfer based high-level synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
High-level synthesis under multi-cycle interconnect delay
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Behavior-to-placed RTL synthesis with performance-driven placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Coupling-aware high-level interconnect synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Architecture and synthesis for multi-cycle on-chip communication
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Resource Sharing Combined with Layout Effects in High-Level Synthesis
Journal of VLSI Signal Processing Systems
Platform-based resource binding using a distributed register-file microarchitecture
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Distributed register-file microarchitecture (DRFM) which comprises multiple uniform blocks (called islands), each containing a dedicated register file, functional unit(s) and data-routing logic, has been known as a very attractive architecture for implementing designs with platform-featured on-chip memory or register-file IP blocks. In comparison with the discrete-register based architecture, DRFM offers a higher degree of opportunity of reducing the cost of global (inter-island) connections by confining as many the computations to the inside of the islands as possible. Consequently, for DRFM architecture, two important problems to be solved effectively in high-level synthesis are: (problem 1) scheduling and resource binding for minimizing inter-island connections, and (problem 2) data transfer (i.e., communication) scheduling through the inter-island connections for minimizing the access conflicts among the data transfers. This work proposes novel solutions to the two problems. Specifically, for problem 1 previous work solves it in two separate steps: (i) scheduling and (ii) then determining the inter-island connections by resource binding to islands. However, in our algorithm called DFRM-int, we place primary importance on the cost of interconnections. Consequently, we minimize the cost of interconnections first to fully exploit the effects of scheduling on interconnect and then to schedule the operations later. For problem 2, previous work tries to solve the access conflicts by forwarding data directly to the destination island. However, in our algorithm called DFRM-com, we devise an efficient technique of exploring an extensive design space of data forwarding indirectly as well as directly to find a near-optimal solution. By applying our proposed synthesis approach DFRM-int+DFRM-com we are able to reduce the inter-island connections by 18.1% more, compared to that by the DRFM approach in [4], even completely eliminating register-file access conflicts, which could never been resolved by [4], without any latency increase.