Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Automatically characterizing large scale program behavior
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
Compact thermal modeling for temperature-aware design
Proceedings of the 41st annual Design Automation Conference
The Case for Lifetime Reliability-Aware Microprocessors
Proceedings of the 31st annual international symposium on Computer architecture
Accurate Energy Dissipation and Thermal Modeling for Nanometer-Scale Buses
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An accurate interconnect thermal model using equivalent transmission line circuit
Proceedings of the Conference on Design, Automation and Test in Europe
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Higher-than-normal wire temperatures and temperature gradients between the sending and receiving ends of a wire that are caused due to Joule heating and substrate hotspots affect the propagation delay of a wire significantly. In this paper, we develop a high-level model to track wire temperatures and delay variability during early stage design exploration. Results using our model show that ALU result bus wires in a 4-issue processor are likely to reach temperatures as high as 103°C (117°C) in 130-nm (45-nm) technology which is greater than the 100°C maximum normally assumed during interconnect design. For a 130-nm processor with no power and thermal management, the temperature-induced timing violations in the ALU result bus, on average across ten SPEC CPU2K benchmarks, is 2.27 per hundred bus references and it can be as high as 4.91 per hundred bus references in some programs. It increases to an average of 6.20 per hundred bus references for the same processor at the 45-nm technology node.