A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Exploiting multiple functionality for nano-scale reconfigurable systems
Proceedings of the 13th ACM Great Lakes symposium on VLSI
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Proceedings of the 2004 international workshop on System level interconnect prediction
VLSI implementations of threshold logic-a comprehensive survey
IEEE Transactions on Neural Networks
Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS
IEEE Transactions on Neural Networks
Real-Time Reconfigurable Subthreshold CMOS Perceptron
IEEE Transactions on Neural Networks
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We present a compact and error tolerant implementation of reconfigurable threshold logic gates (TLG) based on nanoscale DG-MOSFET transistors. The use of independently driven double-gate (IDDG) MOSFETs to build a TLG leads not only to fine-grain reconfigurability by way of voltage-adjustable threshold level (T), but also allows one to vary input weights (w i ) or reduce number of inputs (x i ), depending on the design preferences. Operation of the proposed TLG circuits is verified using UFDG SPICE model, and design trade-offs in terms of size, functionality and performance are also indicated. We show that IDDG MOSFETs lead to more efficient and compact TLG circuits that have better design latitude and noise immunity than the conventional counterparts, while also improving the overall reconfigurability. When the back-gate dynamic threshold adjustment afforded by the ultra-thin (T and can simplify TLG circuit design.