Efficient message management in tiled CMP architectures using a heterogeneous interconnection network

Authors:
Antonio Flores;Juan L. Aragón;Manuel E. Acacio
Affiliations:
Departamento de Ingeniería y Tecnología de Computadores, University of Murcia, Murcia, Spain;Departamento de Ingeniería y Tecnología de Computadores, University of Murcia, Murcia, Spain;Departamento de Ingeniería y Tecnología de Computadores, University of Murcia, Murcia, Spain
Venue:
HiPC'07 Proceedings of the 14th international conference on High performance computing
Year:
2007

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Abstract

Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has significant impact on both overall performance and energy consumption. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth and power characteristics. In this work, we present a proposal for performance-and energy-efficient message management in tiled CMPs by using a heterogeneous interconnect. Our proposal consists of Reply Partitioning, a technique that classifies all coherence messages into critical and short, and non-critical and long messages; and the use of a heterogeneous interconnection network comprised of low-latency wires for critical messages and low-energy wires for non-critical ones. Through detailed simulations of 8- and 16-core CMPs, we show that our proposal obtains average improvements of 8% in execution time and 65% in the Energy-Delay2 Product metric of the interconnect over previous works.