The Journal of Supercomputing
HiPC'07 Proceedings of the 14th international conference on High performance computing
Efficient and scalable barrier synchronization for many-core CMPs
Proceedings of the 7th ACM international conference on Computing frontiers
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Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessors (CMPs) constitute the architecture of choice in the high performance embedded domain for sev- eral reasons such as better levels of scalability and perfor- mance/energy ratio. On the other hand, higher clock fre- quencies and increasing transistor density have revealed power dissipation as a critical design issue, especially in embedded systems where reduced energy consumption di- rectly translates into extended battery life. In this work we present Sim-PowerCMP, a detailed architecture-level power-performance simulation tool for CMP architectures that integrates several well-known contemporary simula- tors (RSIM, HotLeakage and Orion) into a single frame- work. As a case of use of Sim-PowerCMP, we present a characterization of the energy-efficiency of a CMP for par- allel scientific applications, paying special attention to the energy consumed on the interconnect. Results for an 8- and 16-core CMP show that the contribution of the interconnec- tion network to the total power is close to 20%, on average, and that the most consumingmessages are replies that carry data (almost 70% of total energy consumed in the intercon- nect).