On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Performance-impact limited area fill synthesis
Proceedings of the 40th annual Design Automation Conference
Interconnect and noise immunity design for the Pentium 4 processor
Proceedings of the 40th annual Design Automation Conference
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Study of Floating Fill Impact on Interconnect Capacitance
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A layout dependent full-chip copper electroplating topography model
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Pessimism reduction in crosstalk noise aware STA
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Design for Manufacturability and Yield for Nano-Scale CMOS
Design for Manufacturability and Yield for Nano-Scale CMOS
Dummy fill density analysis with coupling constraints
Proceedings of the 2007 international symposium on Physical design
Fill for shallow trench isolation CMP
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Energy-Minimization Model for Fill Synthesis
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
TROY: track router with yield-driven wire planning
Proceedings of the 44th annual Design Automation Conference
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Capacitive coupling noise in high-speed VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMP Fill Synthesis: A Survey of Recent Studies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Closed-form expressions for the coupling capacitance of metal fill tiles in VLSI circuits
Microelectronics Journal
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In this paper, we investigate the crosstalk-induced delay, noise, and chemical mechanical polishing (CMP)-induced thickness-variation implications of dummy fill generated using rule-based wire track fill techniques and CMP-aware model-based methods for designs implemented in 65 nm process technology. The results indicate that fill generated using rule-based and CMP-aware model-based methods can have a significant impact on parasitic capacitance, interconnect planarization, and individual path delay variation. Crosstalk-induced delay and noise are significantly reduced in the grounded-fill cases, and designs with floating fill also experience a reduction in average crosstalk-induced delay and noise, which is in contrast to the predictions of previous studies on small-scale interconnect structures. When crosstalk effects are included in the analysis, the observed delay behavior is significantly different from the delay modeled without considering crosstalk effects. Consequently, crosstalk-induced delay and noise must be simultaneously considered in addition to parasitic capacitance and interconnect planarization when developing future fill generation methods