Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling

Authors:
Won-Seok Lee;Keun-Ho Lee;Jin-Kyu Park;Tae-Kyung Kim;Young-Kwan Park;Jeong-Taek Kong
Affiliations:
-;-;-;-;-;-
Venue:
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Year:
2003

Citing 0
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Abstract

In this paper, the influence of floating dummy metal-fillson interconnect parasitic is analyzed with the variationsof possible factors which can affect the capacitance.Recently proposed chip-level metal-fill modeling, replacingmetal-fill layer with effective high-k dielectric, hasbeen reviewed in detail. Using a systematized modelingflow, the property of the effective permittivity in the modeledgeometry is examined. Validation with the realistic3D structures clearly demonstrates the importance andcorrectness of the geometry modeling.