Reticle enhancement technology: implications and challenges for physical design
Proceedings of the 38th annual Design Automation Conference
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 2005 international symposium on Physical design
CMP aware shuttle mask floorplanning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
BoxRouter: a new global router based on box expansion and progressive ILP
Proceedings of the 43rd annual Design Automation Conference
Dummy fill aware buffer insertion during routing
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Wire density driven global routing for CMP variation and timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A methodology for fast and accurate yield factor estimation during global routing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Metal-density driven placement for cmp variation and routability
Proceedings of the 2008 international symposium on Physical design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
Proceedings of the 45th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dummy fill optimization for enhanced manufacturability
Proceedings of the 19th international symposium on Physical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Physical design techniques for optimizing RTA-induced variations
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Journal of Intelligent Manufacturing
Techniques for scalable and effective routability evaluation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Chemical-mechanical polishing (CMP) is an enabling technique used in deep-submicrometer VLSI manufacturing to achieve long range oxide planarization. Post-CMP oxide topography is highly related to local pattern density in the layout. To change local pattern density and, thus, ensure post-CMP planarization, dummy features are placed in the layout. Based on models that accurately describe the relation between local pattern density and post-CMP planarization by Stine et al. (1997), Ouma et al. (1998), and Yu et al. (1999), a two-step procedure of global density assignment followed by local insertion is proposed to solve the dummy feature placement problem in the fixed-dissection regime with both single-layer and multiple-layer considerations. Two experiments conducted with real design layouts gave excellent results by reducing simulated post-CMP topography variation from 767 Å to 152 Å in the single-layer formulation and by avoiding cumulative effect in the multiple-layer formulation. The simulation result from single-layer formulation compares very favorably both to the rule-based approach widely used in industry and to the algorithm by Kahng et al (1999). The multiple-layer formulation has no previously published work