Design for manufacturability in submicron domain
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Practical iterated fill synthesis for CMP uniformity
Proceedings of the 37th Annual Design Automation Conference
Monte-Carlo algorithms for layout density control
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
New and Exact Filling Algorithms for Layout Density Control
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Optimizing yield in global routing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A New Flexible Algorithm for Random Yield Improvement
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Early probabilistic noise estimation for capacitively coupled interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, a novel and computationally efficient methodology to accurately estimate key yield factors during the global routing stage is presented. Such an yield factor estimator at the global routing stage is essential since it can used to either get an early estimate of the final yield of the same design (i.e. the yield after applying the required sequence of detailed routing and post-routing yield optimizations) and/or to improve the final yield of the design by making the solution at the end of global routing more amenable to post-routing yield optimizations. The proposed yield factor estimator is inherently flexible and can easily be programmed to estimate during global routing a variety of key yield factors of the same design after a typical sequence of detailed routing and representative post-routing yield optimizations has been applied. Examples are provided to show how the yield factor estimator can be used to predict short and open critical area and metal density after typical yield optimization solutions like wire-spreading, wire-widening and metal filling, respectively. Experimental results presented in the paper show that the proposed yield factor estimator can predict final yield factor hotspots/values with a high degree of accuracy. The proposed estimator is also shown to be more suited for the purpose of yield factor estimation compared with typical metrics at the global routing stage like congestion.