Dummy fill aware buffer insertion during routing

Authors:
Yanming Jia;Yici Cai;Xianlong Hong
Affiliations:
Tsinghua University, Beijing, UNK, China;Tsinghua University, Beijing, UNK, China;Tsinghua University, Beijing, UNK, China
Venue:
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Year:
2007

Citing 7
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Abstract

This paper studies the impacts of dummy fill for chemical mechanical polishing (CMP)-induced capacitance variation on buffer insertion during routing. Compared with existing methods, our algorithm is more feasible by performing buffer insertion not in post-process but during routing. Our contributions are threefold. First, we introduce a fast dummy fill estimation algorithm based on [4], which is better than traditional linear programming (LP) algorithm and suitable for early estimation. Second, based on some reasonable assumptions, we present an optimum virtual dummy fill method to estimate dummy position and the effects on the interconnect capacitance. Third, further analysis shows that the influences on the intermediate layer are more than that on the global layer, and as the required metal layer density increases the influences become more serious. Experiments gave the similar results and verified the necessity of early dummy fill estimation. Our dummy fill aware buffer insertion during early routing is promising and necessary.