The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
Proceedings of the 37th Annual Design Automation Conference
A novel framework for multilevel routing considering routability and performance
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Probabilistic congestion prediction
Proceedings of the 2004 international symposium on Physical design
A layout dependent full-chip copper electroplating topography model
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Dummy fill aware buffer insertion during routing
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Wire density driven global routing for CMP variation and timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
CMP-aware Maze Routing Algorithm for Yield Enhancement
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Novel wire density driven full-chip routing for CMP variation control
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Pattern routing: use and theory for increasing predictability and avoiding coupling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MR: a new framework for multilevel full-chip routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dummy fill optimization for enhanced manufacturability
Proceedings of the 19th international symposium on Physical design
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Topography variation has a significant impact on performance as well as printability for nanometer technologies. In this paper, we propose an improved full-chip routing system for reducing Cu CMP (Chemical Mechanical Polishing) & ECP (Electroplating) topology variation, in which CMP aware global routing, CMP aware layer assignment and ECP aware detailed routing are integrated. To the best of our knowledge, this is the first work to consider both Cu CMP and ECP variation all through routing procedure. First, a Cu CMP and ECP topology model considering both perimeter density and feature density is used in global routing, layer assignment and detailed routing to guide the whole optimization procedure. Second, a W-shape multilevel routing model is applied to fully control topology variation from a macroscopic level to a microscopic level. Third, layer assignment which plays a key role in trading off the density between interlayer and intralayer, is integrated into the multilevel routing system and a fast simulated annealing based algorithm is presented to take additive effect on multiple layers into consideration. Experiments show that the proposed algorithm can reduce 6%-7% post-ECP variation and 15%-17% post-CMP variation on average than CMP-aware detailed routing algorithm in [5]. Furthermore, it can insert smaller amount (about 5%) of dummy fill, which means less impact on performance.