Impact of Modern Process Technologies on the Electrical Parameters of Interconnects

Authors:
Debjit Sinha;Jianfeng Luo;Subramanian Rajagopalan;Shabbir Batterywala;Narendra V. Shenoy;Hai Zhou
Affiliations:
Northwestern University, Evanston, IL;ATG, Synopsys Inc., Mountain View, CA 94085, USA;ATG, Synopsys India Pvt. Ltd., Bangalore, India;ATG, Synopsys India Pvt. Ltd., Bangalore, India;ATG, Synopsys Inc., Mountain View, CA 94085, USA;Northwestern University, Evanston, IL
Venue:
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Year:
2007

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Abstract

This paper presents the results obtained from an experimental study of the impact of modern process technologies on the electrical parameters of interconnects. Variations in parasitic capacitances and resistances due to dummy metal fills, chemical mechanical polishing, multiple thin inter-layer dielectrics and trapezoidal conductor crosssections are presented. Accurate variations in the parasitics are reported for a set of timing critical nets using 3d field solvers for extraction. Results obtained on a set of industrial designs show that the impact of dummy fills and trapezoidal conductor cross-sections are significant.