Thermal-Aware Floorplanning Using Genetic Algorithms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Introduction to Genetic Algorithms
Introduction to Genetic Algorithms
Variability analysis under layout pattern-dependent rapid-thermal annealing process
Proceedings of the 46th Annual Design Automation Conference
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Area fill synthesis for uniform layout density
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMP Fill Synthesis: A Survey of Recent Studies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In deep sub-micron era, many semiconductor fabrication process variations highly relate to uniformity of IC layout design. Chemical-polishing process and Flash Lamp Anneal (FLA) are two of the crucial processes aiming to increase uniformity of IC. Dummy filling is an efficient and effective Design for Manufacturability method for increasing layout uniformity by filling non-functional dummy shapes onto unoccupied area and thus reducing pattern-induced process variation. However, none are design for the thermal effects of FLA process. FLA process annealed the wafer in high temperature (1250°C) in a few milliseconds. Wafer surface emissivity determines the amount of heat absorption during FLA process. The temperature variation of FLA process induced by surface emissivity variation of IC layout results in shifts of transistors' electrical parameters. This paper proposed to use genetic algorithm to minimize the emissivity variation of IC layout by filling a series of prescribed dummy patterns with various emissivity. The experimental results from twenty test cases show that 35% emissivity variation reductions can be achieved and moreover the observed temperature deviation during FLA is under 2.8%.