Some Thoughts on the IC Design-Manufacture Interface
IEEE Design & Test
Process variation aware OPC with variational lithography modeling
Proceedings of the 43rd annual Design Automation Conference
A unified non-rectangular device and circuit simulation model for timing and power
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A pixel-based regularization approach to inverse lithography
Microelectronic Engineering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On linewidth-based yield analysis for nanometer lithography
Proceedings of the Conference on Design, Automation and Test in Europe
Exact closed-form expressions for substrate resistance and capacitance extraction in nanoscale VLSI
Microelectronics Journal
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With lithography parameters approaching their limits, continuous improvement requires increasing dialogues and compromises between the technology and design communities. Only with such communication can semiconductor manufacturers reach the 30-nm physical-gate-length era with optical lithography.