Filling and slotting: analysis and algorithms
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Rapid profiling via stratified sampling
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Comments on "Filling algorithms and analyses for layout density control"
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMP Fill Synthesis: A Survey of Recent Studies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Lithographic variability and its impact on printability is a major concern in today's semiconductor manufacturing process. To address sub-wavelength printability, a number of resolution enhancement techniques (RET) have been used. While RET techniques allow printing of sub-wavelength features, the feature width itself becomes highly sensitive to process parameters, which in turn detracts from yield due to small perturbations in manufacturing parameters. Yield loss is a function of random variables such as depth-of-focus and exposure dose. In this paper, we present a first order canonical dose/focus model that takes into account both the correlated and independent randomness of the effects of lithographic variation. A novel tile-based yield estimation technique for a given layout, based on a statistical model for process variability is presented. Another novel contribution of this paper is the computation of global and local line-yield probabilities. The key issues addressed in this paper are (i) layout error modeling, (ii) avoidance of mask simulation for chip layouts, (iii) avoidance of full Monte-Carlo simulation for variational lithography modeling, (iv) building a methodology for yield estimation based on existing commercial tools. Numerical results based on our approach are shown for 45nm ISCAS85 layouts.