A unified non-rectangular device and circuit simulation model for timing and power

Authors:
Sean X. Shi;Peng Yu;David Z. Pan
Affiliations:
The University of Texas at Austin, Austin, TX;The University of Texas at Austin, Austin, TX;The University of Texas at Austin, Austin, TX
Venue:
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Year:
2006

Citing 5
Cited 7

MOSFET Models for VLSI Circuit Simulation: Theory and Practice

MOSFET Models for VLSI Circuit Simulation: Theory and Practice
Design Challenges of Technology Scaling

IEEE Micro
Microlithography: Trends, Challenges, Solutions, and Their Impact on Design

IEEE Micro
Advanced timing analysis based on post-OPC extraction of critical dimensions

Proceedings of the 42nd annual Design Automation Conference
Process variation aware OPC with variational lithography modeling

Proceedings of the 43rd annual Design Automation Conference

Modeling and analysis of non-rectangular gate for post-lithography circuit simulation

Proceedings of the 44th annual Design Automation Conference
A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A framework for early and systematic evaluation of design rules

Proceedings of the 2009 International Conference on Computer-Aided Design
Performance-based optical proximity correction methodology

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of the nonrectangular gate effect for postlithography circuit simulation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correction

Proceedings of the 49th Annual Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

For 65nm and below devices, even after optical proximity correction (OPC), the gate may still be non-rectangular. There are several limited works on the device and circuit characterizations for the post-OPC non-ideal-shape wafer images, with significant impacts on timing and power. Most of them, however, are based on the equivalent gate length models, which are different for timing and leakage, and thus hard to use for coherent circuit simulations. In this paper, we propose a unified post-litho device characterization model and circuit simulation for timing and power. To our best knowledge, this is the most accurate methodology for post-litho analysis, including timing, leakage and transient simulation. Based on this method, the parameter extraction is also included in the model which was omitted by previous works. A post-litho model card is proposed for circuit simulation to combine these two techniques. Our experimental results validate the new model.