ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
RADAR: RET-aware detailed routing using fast lithography simulations
Proceedings of the 42nd annual Design Automation Conference
Standard cell characterization considering lithography induced variations
Proceedings of the 43rd annual Design Automation Conference
A unified non-rectangular device and circuit simulation model for timing and power
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Modeling and analysis of non-rectangular gate for post-lithography circuit simulation
Proceedings of the 44th annual Design Automation Conference
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For nanoscale CMOS devices, gate roughness has severe impact on the device I-V characteristics, particularly in the subthreshold region. In particular, the nonrectangular gate (NRG) geometries are caused by subwavelength lithography and have relatively low spatial frequency. In this paper,we present an analytical approach to modelNRGeffects on I-V characteristics.To predict the change of I-V characteristicsdueto theNRG effect, the proposed model converts the postlithography gate profile into an equivalent gate length (Le), which is a function of the gate bias voltage but independent of the drain bias voltage.We demonstrate the accuracy of this approach by comparing it toTCADsimulation results for65-nmtechnology. The new Le model is readily integrated into standard transistor models in traditional circuit simulation tools, such as SPICE, for both dc and transient analyses. We further develop a generic procedure to systematically extract the Le value fromthe postlithographygateprofile.The interaction with the narrow-width effect is also efficiently incorporated into the proposed algorithm. TCAD verification demonstrates that the proposed Le model is simple for implementation, scalable with both transistor geometriesandbias conditions, and also continuous across all the operation regions.